The Square Kilometre Array Project is the largest mega-science project of the next decade. It presents numerous computing challenges, particularly in its central signal processor that will process terabytes of incoming data every second, and in its science data processor with Exascale compute requirements. This talk will outline the key tasks for which FPGA and other accelerators are being considered and some designs that seek to overcome the limitations of current technologies.
Dr Andrew Ensor is the Director of the High Performance Computing Research Laboratory at AUT University. His research interests include HPC and GPU computing, distributed and mobile system, algorithms, concurrency and computer graphics. Andrew is also the Director of the New Zealand Alliance, a group of over thirty NZ academic and industry partners working on the Exascale computer design for the Square Kilometre Array Project.
Energy is the key limiter to all computations today---both cloud and mobile. This represents an opportunity and demand for Field-Programmable Technologies. Compared to traditional processors (and, perhaps, even ASICs), FPTs have a number of inherent energy advantages. Configurability allows FPTs to (1) perform fewer operations and (2) reduce operating voltages despite the high process variation and aging effects of highly scaled technologies. The spatial design of FPTs (3) eliminates (or reduces) instruction energy, (4) reduces switching activity, and (5) reduces communication distances. In this talk we review the fundamental origin of these phenomena to better understand the FPT energy advantage and its potential. This suggests both directions to refine our FPT architectures to further maximize the advantage and opportunities to craft our FPT applications to minimize energy consumption.
Andre DeHon received S.B., S.M., and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 1990, 1993, and 1996 respectively. From 1996 to 1999, Andre co-ran the BRASS group in the Computer Science Department at the University of California at Berkeley. From 1999 to 2006, he was an Assistant Professor of Computer Science at the California Institute of Technology. In 2006 he joined the Electrical and Systems Engineering Department at the University of Pennsylvania, where he is now a Full Professor. He is broadly interested in how we physically implement computations from substrates, including VLSI and molecular electronics, up through architecture, CAD, and programming models. He places special emphasis on spatial programmable architectures (e.g. FPGAs) and interconnect design and optimization.
As FPGAs grow ever larger and include more diverse and high-speed blocks like high-speed memory interfaces and processor subsystems, the task of connecting all the modules in a design with traditional low-level FPGA interconnect is becoming ever more time-consuming and difficult.
Furthermore, to expand FPGA use to new domains like the data center, faster design times and easy integration of components, including at run time with partial reconfiguration, are highly desirable. This talk will discuss how Networks-on-Chips can be incorporated into FPGAs as a new type of hard block, and can shorten design time, improve hardware efficiency, and simplify advanced CAD flows like partial reconfiguration. We will show how different design styles and applications can be mapped to and benefit from this new interconnect. We will outline progress to date on an automated CAD flow to simplify use of such structures, and some of the remaining challenges. Finally, we'll look at how recent trends in FPGA architecture and end markets - the interest in embedded FPGA fabrics in systems-on-chips, the increasing use of silicon interposers to build FPGA systems, registered interconnect, and the prospect of FPGAs in the data center - impact the case for making this disruptive architecture change.
Vaughn Betz is an Associate Professor at the University of Toronto. Dr. Betz is the creator of the VPR FPGA CAD suite and was a co-founder of Right Track CAD in 1998 and its VP of Engineering until its acquisition by Altera in 2000. He held various roles at Altera from 2000 to 2011, ultimately as Senior Director of Software Engineering, and is one of the architects of both Quartus II and of the Stratix I - V devices. He joined the University of Toronto in 2011, where his research covers FPGA architecture, CAD and FPGA-based computation. Dr. Betz has published extensively on programmable logic and CAD, and has received 9 best or most significant paper awards; he holds 89 US patents in the FPGA area.