Design competition rules
Participating teams will compete against one another in a round-robin competition, with each match consisting of two games, one played as black, and one played as white. Games will follow standard Trax rules (unlimited size of playing area) with the exception that illegal moves will result in immediate loss of game.
Designs must be implemented on a stand-alone FPGA board (i.e. not plugged into a host computer chassis or connected to any other external processor). Development boards containing any of the low to mid-range FPGAs are allowed. There is no restriction on the use of hard or soft core processors in your design.
- Altera devices: any Cyclone, and Arria FPGA.
- Xilinx devices: any Spartan, Artix-7, Kintex-7 and Zync up to Z-7020.
- No Stratix or Virtex devices may be used.
Designs must communicate with the host programme using the RS232 protocol. Communication is in the form of text strings, terminated with a new line. When a new game is started, the FPGA is sent "-W" or "-B" to indicate whether it is playing white or black respectively. The white player should respond with the first move using Trax notation. Thereafter, whenever an FPGA is sent a move, it should respond with a move in reply.
All responses (apart from "-B") must consist of a legal move, made within 1 second. Failure of this will result in forfeiting the game.
Trax notation records the location and orientation of the primary tile played using a 3 part code:
- Alphabetic characters are used to indicate the column, counting from the left of the overall position. "@" is used for the leftmost empty column, followed by "A" to "Z", then "AA" to "AZ". "BA", etc.
- The row is indicated by a number counting from the top of the overall position. "0" is used for the topmost empty row, followed by "1", "2", "3", etc.
- The tile played is represented by "+" for straight tiles, and "/" or "\" for curves according to the orientation of the curved paths on the tile.
The first move of the game is either "@0/" or "@0+".