The 2015 International Conference on

Field-Programmable Technology (FPT '15)

7-9 December, Rydges Lakeland Resort, Queenstown, New Zealand

Accepted Technical Papers and Posters

Oral Session O1: Applications I

  • Accelerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy,
    Junyi Xie, Xinyu Niu, Andy K. S. Lau, Kevin K. Tsia and Hayden K. H. So.
  • FPGA Acceleration of Referential Compression for Genomic Data,
    James Arram, Moritz Pflanzer, Thomas Kaplan and Wayne Luk.
  • Leftmost Longest Regular Expression Matching in Reconfigurable Logic,
    Kubilay Atasu.
  • Bringing Programmability to the Data Plane: Packet Processing with a NoC-Enhanced FPGA,
    Andrew Bitar, Mohamed Abdelfattah and Vaughn Betz.

Oral Session O2: High Level Synthesis, Debugging

  • An Adaptive Virtual Overlay for Fast Trigger Insertion for FPGA Debug,
    Fatemeh Eslami and Steve Wilton.
  • Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs,
    Jeffrey Goeders and Steve Wilton.
  • Using Source-to-Source Compilation to Instrument Circuits for Debug with High Level Synthesis,
    Joshua Monson and Brad Hutchings.

Oral Session O3: Architecture

  • QuickDough: A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay,
    Cheng Liu, Ho-Cheung Ng and Hayden Kwok-Hay So.
  • Energy Minimization in the Time-Space Continuum,
    Hyunseok Park, Shreel Vijayvargiya and Andre Dehon.
  • Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology,
    Alex Rodionov and Jonathan Rose.
  • Improved Carry-Chain Mapping for the VTR Flow,
    Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko and Paolo Ienne.

Oral Session O4:

  • Hetris: Adaptive Floorplanning for Heterogeneous FPGA,
    Kevin E. Murray and Vaughn Betz.
  • Analyzing the Divide between FPGA Academic and Commercial Results,
    Elias Vansteenkiste, Henri Fraisse and Alireza Kaviani.
  • OpenCL Library of Stream Memory Components Targeting FPGAs,
    Jasmina Vasiljevic, Paul Chow, Paul Schumacher, Fernando Martinez Vallina, Ralph Wittig and Jeff Fitfield.
  • Exploring Pipe Implementations using an OpenCL Framework for FPGAs,
    Vincent Mirian and Paul Chow.

Oral Session O5: Applications II

  • An Exact MCMC Accelerator Under Custom Precision Regimes,
    Shuanglong Liu, Grigorios Mingas and Christos-Savvas Bouganis.
  • FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC,
    Jianfeng Zhang, Paul Chow and Hengzhu Liu.
  • Braiding: a Scheme for Resolving Hazards in Kernel Adaptive Filters,
    Stephen Tridgell, Duncan Moss, Nicholas Fraser and Philip Leong.

Oral Session O6: High Level Synthesis II

  • Custom-Sized Caches in Application-Specific Memory Hierarchies,
    Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, John Wickerson and George Constantinides.
  • Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware,
    Jongsok Choi, Stephen Brown and Jason Anderson.
  • Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning,
    Ian Graves, Adam Procter, William Harrison and Gerard Allwein.

Poster Session P1:

  • Automatic framework to generate reconfigurable accelerators for option pricing applications,
    Nam Khanh Pham, Akash Kumar and Khin Mi Mi Aung.
  • Behavioral-Level IP Integration in High-Level Synthesis,
    Liwei Yang, Swathi Gurumani, Deming Chen and Kyle Rupnow.
  • Optimized High-Level Synthesis of SMT Multi-Threaded Hardware Accelerators,
    Jens Huthmann and Andreas Koch.
  • A Real-Time High Resolution SURF on FPGA,
    Xijie Jia, Kaiyuan Guo, Wenqiang Wang, Yu Wang and Huazhong Yang.
  • Minimising DSP Block Usage Through Multi-Pumping,
    Ronak Bajaj and Suhaib A. Fahmy.
  • An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoC,
    Jifang Jin, Jian Yan, Xuegong Zhou and Lingli Wang.
  • A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering,
    Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener and Jürgen Teich.
  • A Self-aware Data Compression System on FPGA in Hadoop,
    Li Yubin, Sun Yuliang, Dai Guohao, Wang Yuzhi, Ni Jiacai, Wang Yu, Li Guoliang and Yang Huazhong.

Poster Session P2:

  • An FPGA-based Real-time Simultaneous Localization and Mapping System,
    Mengyuan Gu, Kaiyuan Guo, Wenqiang Wang, Yu Wang and Huazhong Yang.
  • Hardware Architecture of a Fast, Parallel Random Tree Path Planner,
    Size Xiao, Adam Postula and Neil Bergmann.
  • Lower Precision for Higher Accuracy: Precision and Resolution Exploration for Shallow Water Equations,
    James Targett, Xinyu Niu, Francis Russell, Wayne Luk, Stephen Jeffress and Peter Dueben.
  • Comparison of Thread Signatures for Error Detection in Hybrid Multi-cores,
    Sebastian Meisner and Marco Platzner.
  • Advanced Bayer Demosaicing on FPGA,
    Donald Bailey, Sherry Randhawa and Jimmy Li.
  • Betweenness Centrality-based Suspicious Signal Identification for Hardware Trojan Detection on FPGA,
    He Li and Qiang Liu.
  • Improving Performance of Shuffled Higher-Order Masked AES via Instruction Extension,
    Yi Wang and Yajun Ha.
  • JIT Trace-based Verification for High-Level Synthesis,
    Liwei Yang, Magzhan Ikram, Swathi Gurumani, Deming Chen, Suhaib Fahmy and Kyle Rupnow.

PhD Forum:

  • Cryptographic Techniques in Redundant Number Systems,
    Jason Motha, Andrew Bainbridge-Smith, Steve Weddell
  • 2D Discrete Fourier Transform with Simultaneous Edge Artifact Removal for Real-Time Applications,
    Faisal Mahmood, Mart Toots, Lars-Goran Oversted, Ulf Skoglund
  • FPGA based Acceleration of FDAS Module for Pulsar Search,
    Haomiao Wang, Oliver Sinnen
  • FPGA Implementation of a SIMD-Based Array Processor with Torus Interconnect,
    Yuki Murakami

Demo Session:

  • An Efficient Architecture for Zero Overhead Data En-/Decryption using Reconfigurable Cryptographic Engine,
    Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Ricky Y. K. Kwok
  • Smart Camera for Trax Playing Robot,
    Donald G Bailey

Design Competition:

  • Development of Trax AI using Path and Edge,
    Ryo Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, Kazuya Tanigawa
  • FPGA Trax Solver based on a Neural Network Design,
    Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Masato Seo, Kouta Akagi, Shinya Furukawa, and Minoru Watanabe
  • An Architecture-Algorithm Co-Design of Artificial Intelligence for Trax Player,
    Qing Lu, Bruce Chiu-Wing Sham,
  • An Implementation of Trax Player using Programmable SoC,
    Akira Kojima
  • Trax Solver on Zynq with Deep Q-Network,
    Naru Sugimoto, Takuji Mitsuishi, Chiharu Tsuruta, Takahiro Kaneda, Ryotaro Sakai, Hideharu Amano
  • High Speed TRAX Player on FPGA,
    Hossein Borhanifar